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2 Mbit SPI Serial Flash
A Microchip Technology Company
SST25LF020A
Not Recommended for New Designs
High-Speed-Read (33 MHz)
The High-Speed-Read instruction supporting up to 33 MHz is initiated by executing an 8-bit command,
0BH, followed by address bits [A 23 -A 0 ] and a dummy byte. CE# must remain active low for the duration
of the High-Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy byte (8 clocks input dummy cycle), the High-Speed-Read instruction outputs the
data starting from the specified address location. The data output stream is continuous through all
addresses until terminated by a low to high transition on CE#. The internal address pointer will auto-
matically increment until the highest memory address is reached. Once the highest memory address is
reached, the address pointer will automatically increment to the beginning (wrap-around) of the
address space, i.e. for 2 Mbit density, once the data from address location 03FFFFH has been read,
the next output will be from address location 000000H.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
SCK
MODE 0
SI
0B
ADD.
ADD.
ADD.
X
MSB
MSB
SO
HIGH IMPEDANCE
N
D OUT
N+1
D OUT
N+2
D OUT
N+3
D OUT
N+4
D OUT
MSB
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V IL or V IH )
1242 F05.0
Figure 6: High-Speed-Read Sequence
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A 23 -A 0 ]. Following the address, the data is
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status register or wait T BP for the completion of
the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39
SCK
MODE 0
SI
MSB
02
ADD.
MSB
ADD.
ADD.
D IN
MSB
LSB
SO
HIGH IMPEDANCE
1242 F06.0
Figure 7: Byte-Program Sequence
?2011 Silicon Storage Technology, Inc.
11
DS25080A
11/11
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